编写一个序列检测模块，检测输入信号（a）是否满足011100序列， 要求以每六个输入为一组，不检测重复序列，例如第一位数据不符合，则不考虑后五位。一直到第七位数据即下一组信号的第一位开始检测。当信号满足该序列，给出指示信号match。当不满足时给出指示信号not_match。

模块的接口信号图如下

代码如下：

（CSDN代码块不支持Verilog，代码复制到notepad++编辑器中，语言选择Verilog，看得更清楚）

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
	//空闲为什么都没有的状态,S0。
	parameter S0=3'd0,S1=3'd1,S2=3'd2,S3=3'd3,S4=3'd4,S5=3'd5,S6=3'd6,S_FAIL=3'd7;
reg [2:0] state_c,state_n;
reg [2:0]cnt;
always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        state_c <= S0;
    else 
        state_c <= state_n;
end
always@(*)begin
    if(!rst_n)
        state_n = S0;
    else begin
        case(state_c)
            S0: state_n=data?S_FAIL:S1;//0
			S1: state_n=data?S2:S_FAIL;//1
            S2: state_n=data?S3:S_FAIL;//1
            S3: state_n=data?S4:S_FAIL;//1
            S4: state_n=(~data)?S5:S_FAIL;//0
            S5: state_n=S0;//0
            S_FAIL:begin
                    if(cnt==3'd4)
                    state_n=S0;
                    else
                    state_n=S_FAIL;
            end 
            default:state_n = S0;
        endcase
    end
end
always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
        match <= 1'd0;
    else if(state_c == S5 && (~data))
         match <= 1'd1;
    else 
        match <=1'd0;
end
always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
        not_match <= 1'd0;
    else if(state_c == S_FAIL && cnt==3'd4)
         not_match <= 1'd1;
    else 
        not_match <=1'd0;
end
always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
        cnt <= 3'd0;
    else if(state_c == S0)
         cnt <= 3'd0;
    else 
        cnt <=cnt +'d1;
end
endmodule